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  • دکتری (1386)

    مهندسی برق

    دانشگاه تهران، ایران

  • کارشناسی‌ارشد (1378)

    مهندسی برق - الکترونیک

    دانشگاه صنعتی شریف،

  • کارشناسی (1376)

    مهندسی برق - الکترونیک

    دانشگاه صنعتی شریف،

  • طراحی مدارهای مجتمع آنالوگ و دیجیتال فرکانس بالا (RFIC)
  • طراحی فرستنده– گیرنده ‌های مخابراتی‌
  • مدارات و سیستم های مجتمع الکترونیکی برای کاربردهای ایمپلنت پزشكی
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Wideband Inductorless True Time Delay Cell Based on CMOS Inverter for Timed Array Receivers

Ahmad Yarahmadi, Abumoslem Jannesari
Journal PapersCircuits, Systems, and Signal Processing , 2021 March 4, {Pages 24-Jan }

Abstract

In this paper, an inverter-based true time delay (TTD) cell for timed array receivers is proposed. The proposed TTD cell is designed in TSMC 0.18 ?m CMOS technology for multi-GHz operations. The delay cell is made from an all-pass filter by Pad? approximation. The first-order all-pass filter is built by combining a constant gain stage and a low pass stage based on the approximation. The constant gain stage consists of two NMOS transistors. The low pass stage is created with an inverter cell, cascaded with a PMOS transistor. Active true time delay cells are used in delay lines (commonly in cascaded topology) to develop a timed array system. Because of that, size of the TTD cell is critical and is an important design factor. So in this paper,

Diagnosis of Valvular Heart Disease Based on Ensemble Learning

Banafshe Ghardashbegi, Abumoslem Jannesari
Journal PapersComputational Intelligence in Electrical Engineering , Volume 12 , Issue 1, 2021 March 21, {Pages 14-Jan }

Abstract

Heart sound signal processing consists of different phases. After applying necessary preprocessing and segmenting heart sound cycles, some distinctive features of heart sound are extracted. Since the appropriate operation of the classifier has a high impact on the performance of the system, in this study we propose a proper classification algorithm. One of the commonly used methods to build accurate classifiers is to use a group of classifiers and make decision based on the outputs of these classifiers. By far, the performance of the ensemble methods has been investigated in different fields of classification problems by researchers. However, in the field of heart valve diagnosis there are almost no studies investigating these methods. In t

High-Q, High-Rejection Ratio Complex Second-Order Charge-Sampling Switched - Semi-Passive Band-Pass Filter

MS Jafari, A Jannesari
Journal Papers , , {Pages }

Abstract

A Higher-Order Highly Linear N-Path Band-Pass Filter

Akbar Hemati, Abumoslem Jannesari
Journal PapersCircuits, Systems, and Signal Processing , 2020 June 25, {Pages 20-Jan }

Abstract

This paper proposes a higher-order fully passive N-path filter (HOFPNF) with better pass-band shape and higher out-of-band rejection compared with the conventional N-path filter. Two band-pass filters with slightly different center frequencies are constructed using two frequency mixers and two complex filters which are completely composed of switches and capacitors. The final output of the HOFPNF can be obtained by subtracting the outputs of these two filters. The input–output characteristic of the proposed filter is derived using the Fourier transform. Comparing the theoretical expressions with Spectre RF PSS-PAC simulation results verifies the correctness of the derived transfer function. The system is realized at TSMC 0.18 ?m technolog

Cell Weighting and Gate Inductive Peaking Techniques for Wideband Noise Suppression in Distributed Amplifiers

Baset Mesgari, Saeed Saeedi, Abumoslem Jannesari
Journal PapersIEEE Transactions on Circuits and Systems I: Regular Papers , 2020 July 7, {Pages }

Abstract

This paper presents a noise suppression method to improve noise figure (NF) performance of a distributed amplifier (DA) in a broad frequency range. In the proposed DA topology, the input matching resistor, which remarkably increases the NF, is replaced by a common-gate (CG) stage. The noise contribution of the CG terminating network is suppressed by employing a cell weighting plan in conjunction with a gate-inductive peaking technique. Analytical methods and a circuit implementation in a 0.18 μm CMOS technology verify that the proposed noise suppression technique provides lower NF compared with the conventional DA (CDA) topology in the entire frequency range. This is in contrast to other reported low-noise DA topologies which decrease the

A Double Balanced Mixer with Folded Structure and Variable-Conversion gain in 65nm CMOS

Mohammad Reza Nikbakhsh, Abumoslem Jannesari, Ebrahim Abiri, Sanaz Salem
Conference Papers2020 28th Iranian Conference on Electrical Engineering (ICEE) , 2020 August 4, {Pages 05-Jan }

Abstract

In this paper, a mixer with radio frequency (RF) input signal in the range of 9.5GHz to 10.5GHz and intermediate frequency (IF) in the range of 0.5GHz to 1.5GHz is designed. The proposed mixer has the variable conversion gain that not only ensures the appropriate performance of the system in face with large signals, but also increases the dynamic range of the receiver. With novel structure, the gain variation of sub-blocks does not destroy the other system parameters. In the proposed circuit, the PMOS switches are selected in order to improve the design of variable conversion gain and decrease its flicker noise. By DC coupling, the first stage, in which convert the RF voltage into current, is separated from the switching stage that cause th

High-Q, high-rejection ratio complex second-order charge-sampling switched gm-C semi-passive band-pass filter

Mohammad Shayan Jafari, Abumoslem Jannesari
Journal PapersJournal of Circuits, Systems and Computers , 2020 December 31, {Pages }

Abstract

In this paper, a complex second-order charge-sampling switched gm-C semi-passive band-pass filter is presented which by using the technique of increasing the number of input signal phases without the need to increase the number of clock phases and switches, has been improved out-ofband rejection, near-band rejection and the quality factor of the filter. In addition to the tunable bandwidth and center frequency that can be tuned independently, the proposed filter provides a very high linearity and consumes low power. Designed and simulated in a 0.18-?m standard CMOS technology, this filter operating at 1GS/s sampling rate has an adjustable center frequency of 11.68-28.5 MHz and a tunable bandwidth of 1.8-8.74 MHz. Also, the out-of-band rejec

Charge-sharing bandpass filter with independent bandwidth and centre frequency adjustment

H Ganji, A Jannesari, Z Sohrabi
Journal PapersElectronics Letters , Volume 55 , Issue 11, 2019 April 18, {Pages 638-640 }

Abstract

A semi-passive charge-sharing complex bandpass filter employing positive feedback technique is proposed to control bandwidth at different centre frequencies. In contrast to the previous arts, bandwidth can be changed independent of centre frequency without any rise in the number of clock phases and switches. Also, insightful continuous-time model and block diagram of the proposed filter have been presented. The results of simulation carried out with 0.18 ?m CMOS technology at 200 MHz reference frequency for centre frequencies of 10 and 20 MHz and bandwidth of 1, 3 and 7 MHz indicate the filter's ability to control the quality factor excellently.

Fast-Transient-Response Low-Voltage Integrated, Interleaved DC–DC Converter for Implantable Devices

Najmeh Cheraghi Shirazi, Abumoslem Jannesari, Pooya Torkzadeh
Journal PapersJournal of Circuits, Systems and Computers , 2019 March 19, {Pages 2050013 }

Abstract

A new self-start-up switched-capacitor charge pump is proposed for low-power, low-voltage and battery-less implantable applications. To minimize output voltage ripple and improve transient response, interleaving regulation technique is applied to a multi-stage Cross-Coupled Charge Pump (CCCP) circuit. It splits the power flow in a time-sequenced manner. Three cases of study are designed and investigated with body-biasing technique by auxiliary transistors: Four-stage Two-Branch CCCP (TBCCCP), the two-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP2) and four-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP4). Multi-phase nonoverlap clock generator circuit with body-biasing technique is also proposed which can operate at voltages as

Noise shaping in low noise amplifiers using active feedback and pole-zero adjustment

Hossein Sahoolizadeh, Abumoslem Jannesari, Massoud Dousti
Journal PapersMicroelectronics Journal , Volume 89 , 2019 July 1, {Pages 15-Jan }

Abstract

In conventional methods, noise calculation of low noise amplifier circuits are performed by eliminating frequency devices or frequency parameters such as inductances and capacitances and only considering the quiescent point. Based on these noise calculation methods, noise figure is evaluated at low frequencies, and this diminishes the accuracy of the calculations. Therefore, in this paper, after extracting full equations of transfer functions of gain and noise, a system of equations is set up. By adjusting different circuit parameters, the frequency responses are adjusted so that in a desired frequency range, the gain assumes its maximum and noise its minimum. In fact, in this way, somehow a noise/gain shaping is realized. Moreover, other c

Design of a Highly Linear Gain Stage with Complementary Derivative Superposition Technique

Ahmad Yarahmadi, Abumoslem Jannesari
Journal PapersWireless Personal Communications , 2019 January , {Pages 08-Jan }

Abstract

In this paper a linearization method called complementary common source derivative superposition (CCS DS) is presented. This structure sets both first and second Derivative of transconductance of the stage to the nearly zero values. So it has a very good performance on both 2nd and 3rd order distortion. It is a biasing scheme to cancel second order and third order distortions of the transistors simultaneously. Both NMOS and PMOS transistors of the strucure are bias in the moderade inversion region. To keep amplifying transistors in the region of interest, a CMFB circuit is used. It makes the circuit robust to the process variations. The structure utilizes the current reuse concept and subsequently the stage provides high enough

High dynamic range pseudo–two‐level digital pulse‐width modulation for power‐efficient RF transmitters

Amir Arian, Abumoslem Jannesari
Journal PapersInternational Journal of Circuit Theory and Applications , Volume 47 , Issue 1, 2019 January , {Pages 65-86 }

Abstract

Radio frequency (RF) power amplification based on pulse‐width modulation (PWM) has been widely discussed as a potential solution to achieve higher efficiency in RF transmitters. A digitally implemented PWM introduces a large amount of in‐band distortion due to spectral aliasing. In this paper, a novel memoryless PWM modulator with a built‐in anti‐aliasing filter is proposed that effectively reduces the in‐band distortion in digital implementation. The spectral characteristics of the proposed PWM modulator as well as the statistical properties of its output PWM signal are analytically studied. The pseudo–two‐level output of the proposed modulator provides the capability to compromise between the efficiency, linearity, and comp

A parasitic insensitive passive switched‐capacitor interpolation finite impulse response filter

Amirreza Nakhi, Abumoslem Jannesari
Journal PapersInternational Journal of Circuit Theory and Applications , 2019 September 2, {Pages }

Abstract

This paper proposes a passive switched‐capacitor (SC) interpolation finite impulse response (IFIR) filter designed with complementary metal‐oxide semiconductor (CMOS) 0.18‐μm technology. Comparing with previous works in analog and digital domain, this filter consumes less power and takes advantage of passive SC circuits, providing high bandwidth and linearity. In addition, offset variation, which is distinctly observed in preceding works, and alteration in the pole, caused by output parasitic capacitance, are no longer present in the proposed filters. Also, a 15‐tap IFIR filter with interpolation factor of 5 has been introduced in the paper, which is able to fully remove the effect of output parasitic capacitance. This filter, whi

Corrigendum to “A 12-bit 100 MS/s pipelined ADC without using front-end SHA” International Journal of Electronics and Communications (AE?) 86 (2018) 142-153

H Imanpoor, M Mehranpouy, P Torkzadeh, A Jannesari
Journal PapersINTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS , Volume 88 , Issue 1, 2018 January 1, {Pages 174-174 }

Abstract

Self-start-up fully integrated DC-DC step-up converter using body biasing technique for energy harvesting applications

N Cheraghi Shirazi, A Jannesari, P Torkzadeh
Journal PapersAEU-International Journal of Electronics and Communications , Volume 95 , 2018 October 1, {Pages 24-35 }

Abstract

An ultra-low power, self-start-up switched-capacitor Two Branch Charge Pump (TBCP) circuit for low power, low voltage, and battery-less implantable applications is proposed. In order to make feasible the low voltage operation, the proposed charge pump along with Non-Overlapped Clock generator (NOC) are designed working in sub-threshold region by using body biasing technique. A four-stage TBCP circuit is implemented with both NMOS and PMOS transistors to provide a direct load flow. This leads to a significant drop in reverse charge sharing and switching loss and accordingly improves pumping efficiency. A post-layout simulation of designed four-stage TBCP has been performed by using an auxiliary body biasing technique. Consequently, a low sta

Noise suppression in a common-gate UWB LNA with an inductor resonating at the source node

Hossein Sahoolizadeh, Abumoslem Jannesari, Massoud Dousti
Journal PapersAEU-International Journal of Electronics and Communications , Volume 96 , 2018 November 1, {Pages 144-153 }

Abstract

In this paper, a noise suppression circuit is proposed and investigated by using resonance technique at the source. Resonance in the source node of the common-gate structure blocks the noise path while transferring the signal from input to output. Through proper analysis, a common gate structure with an active load is improved. As a result, a complementary common gate structure is introduced. A complementary common-gate structure with resonance in the source node can overcome the trade-off between noise and gain in the first stage. Hence, this structure is optimum in terms of the trade-off between gain and noise as well as power dissipation and linearity. Finally, a very-low-noise amplifier is implemented by this method and the post-layout

Power‐efficient burst‐mode RF transmitter based on reference‐adaptive multilevel pulse‐width modulation

Amir Arian, Abumoslem Jannesari
Journal PapersInternational Journal of Circuit Theory and Applications , Volume 46 , Issue 3, 2018 March , {Pages 427-452 }

Abstract

Burst‐mode operation of power amplifier (PA) based on multilevel pulse‐width modulation (MPWM) has been frequently discussed as a potential solution to achieve higher efficiency in radio frequency (RF) transmitters. In this paper, a novel multilevel PWM modulator is proposed that utilizes adaptive triangular reference waveforms. As compared with conventional MPWM modulators, the proposed architecture provides significant wider design space such that the efficiency of system can be effectively optimized. A general transmitter architecture based on the proposed concept is analyzed in terms of power efficiency. Efficiency optimization procedures are presented according to input magnitude statistics. Based on the proposed modulator, an opt

A 12-bit 100 MS/s pipelined ADC without using front-end SHA

H Imanpoor, M Mehranpouy, P Torkzadeh, A Jannesari
Journal PapersAEU-International Journal of Electronics and Communications , Volume 86 , 2018 March 1, {Pages 142-153 }

Abstract

This paper presents a model and a novel architecture of a low-power pipelined analog-to-digital converter (ADC) without using front-end Sample and Hold Amplifier (SHA) stage. The modeling of all ADC building blocks along with their non-ideal effects have been implemented in MATLAB SIMULINK environment and the main transistor level circuits have been implemented in H-SPICE environment using 180-nm TSMC CMOS technology. The maximum DNL and INL amounts are equal to?0.9 LSB and?2.3 LSB, respectively. Applying a 33.1 MHz with 1.4 V p-p (− 6dBFS) input signal, achieved SNDR is 61 dB resulting in 9.8 Bits ENOB with total power consumption of 42 mW.

A Ka-Band Low Phase-Shift CMOS Variable Gain Low Noise Amplifier

Behbid Ali Mohammad Mohammadpour, ABUMOSLEM JANNESARI, Abdolreza Nabavi
Journal Papers , Volume 8 , Issue 400721, 2018 January 1, {Pages 20-Nov }

Abstract

In this paper, a Low Noise Variable Gain Amplifier in Ka-frequency band is designed. This amplifier is digitally controlled by using switching transistors which change the gain with an accuracy of 5-bit resolution (32 steps). The output phase shift should be minimized within a Dynamic Range of 15 dB. The proposed structure includes a Low Noise Amplifier and a Variable Gain Amplifier, with common-source structure and degenerative inductor. In the proposed structure, the main gain is achieved by LNA and the switching control bits are used in two stages of the VGA. Simulation illustrates a Noise Figure of 5. 6 dB; bandwidth of 5. 34 GHz; S11, S22 less than-14 dB and Dynamic Range of 15 dB. By using a “compensating inductor” in the source o

Corrigendum to “A 12-bit 100 MS/s pipelined ADC without using front-end SHA” International Journal of Electronics and Communications (AEÜ) 86 (2018) 142-153

H Imanpoor, M Mehranpouy, P Torkzadeh, A Jannesari
Journal Papers , , {Pages }

Abstract

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